The present invention relates to an MOS circuit and, more particularly, to a semiconductor device having a self substrate bias circuit.
MOS semiconductor integrated circuit devices are being developed for higher packing density, higher speed, and lower power consumption. As a means to achieve these objects, it is generally known to apply a DC bias to the substrate. When DC bias is applied to the substrate of an integrated circuit device, the coupling capacity is reduced, the punch-through voltage is improved, the field leakage is reduced, the noise margin of the input and output waveforms is improved, and the noise margin of the internal circuit is improved. For applying a bias to the substrate, it is generally necessary to apply a DC voltage from outside the integrated circuit device, so an extra pin for connection to the outside is required. The increase in the number of pins for connection to the outside is disadvantageous for integrated circuit devices from the perspective of the manufacturing cost. Thus, efforts have been made to reduce the number of such pins. It is also undesirable from the perspective of the additional power requirement for the system.
A self substrate bias circuit of so-called on-chip type has recently been developed in which the other circuits are formed on a single substrate together with a self substrate bias circuit for generating a DC bias to be applied to the substrate. In such an on-chip type self substrate bias circuit, a distributed capacitor connected between the substrate and a reference voltage source is utilized, and a voltage corresponding to the charge stored in the distributed capacitor becomes the bias voltage to be applied to the substrate. In a conventional self substrate bias circuit, the distributed capacitor is formed by a diffusion region connected to the reference voltage source. Since the area of the diffusion region is limited, a large amount of charge cannot be stored in the distributed capacitor. As a result, the stability of the voltage generated by the self substrate bias circuit is inferior to that obtained with a bias circuit in which a bias voltage is supplied from the outside. On the other hand, when the diffusion area is enlarged, the junction leakage between the substrate and the reference power source increases.
As a capacitor for storing electrons transferred from the self substrate bias circuit, one with a sandwich structure having a pair of conductors with an insulation layer interposed therebetween provides the best storing efficiency. It is possible to form the capacitor of sandwich structure on the same single substrate on which is formed the self substrate bias circuit. However, when forming such a capacitor on the same substrate with the self substrate bias circuit, the chip size becomes extremely large due to the presence of this capacitor, resulting in a higher cost of the device. Further, if a pinhole is formed in the insulation layer of the capacitor of the sandwich structure, not only the capacitor becomes unusable, but the device as well, resulting in increased cost.